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1 copyright ? cirrus logic, inc. 1997 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs4330/31/33 8 pin stereo d/a converter for digital audio features l complete stereo dac system: interpolation, d/a, output analog filtering l 18-bit resolution l 94 db dynamic range l 0.003% thd l low clock jitter sensitivity l single +3 v or +5 v power supply l filtered line level outputs linear phase filtering l on-chip digital de-emphasis description the cs4330, cs4331 and cs4333 are complete, stereo digital-to-analog output systems including interpolation, 1-bit d/a conversion and output analog filtering in an 8- pin package. these devices differ in the serial interface format used to input audio data. the cs4330, cs4331 and cs4333 are based on delta- sigma modulation, where the modulator output controls the reference voltage input to an ultra-linear analog low- pass filter. this architecture allows for infinite adjustment of sample rate between 2 khz and 50 khz while main- taining linear phase response simply by changing the master clock frequency. the cs4330, cs4331 and cs4333 contain on-chip dig- ital de-emphasis, operate from a single +3 v or +5 v power supply, and consume only 60mw of power with a 3 v power supply. these features make them ideal for portable cd players and other portable playback systems. ordering information see page 21. i lrck 3 sdata 1 dem /sclk 2 mclk 4 va+ aoutl 8 aoutr 5 serial input interface interpolator interpolator de-emphasis delta-sigma modulator delta-sigma modulator dac dac voltage reference analog low-pass filter analog low-pass filter 7 agnd 6 may 97 ds136f1
analog characteristics (t a = 25 c; logic "1" = va+; logic "0" = agnd; mclk = 12.288 mhz; full-scale output sine wave, 991 hz; input sample rate = 48 khz; input data = 18 bits; sclk = 3.072 mhz; measurement bandwidth is 10 hz to 20 khz, unweighted; unless otherwise specified. resistive load = 20 k w , capaci- tive load = 100 pf) cs4330/31/33-ks va +5v cs4330/31/33-ks va +3v cs4330/31/33-bs va +5v only parameter symbol min typ max min typ max min typ max units specified temperature range t a -10 to 70 -10 to 70 -40 to +85 c resolution - - 18 - - 18 - - 18 bits dynamic performance dynamic range (a-weighted) 90 94 - - 89 - 88 94 - db total harmonic distortion - 0.003 0.007 - 0.003 - - .003 .008 % total harmonic distortion + noise 0 db output, -20 db output, -60 db output thd+n - - - -86 -72 -32 -81 -68 -28 - - - -85 -67 -27 -80 - - -88 - - -86 -72 -32 -79 -66 -26 db db db deviation from linear phase (note 1) - 0.5 -- 0.5 -- 0.5 -deg passband: to 0.05 db corner (note 2,3) 0 to 21.77 0 to 21.77 0 to 21.77 khz frequency response 10 hz to 20 khz(note 1) - 0.1 -- 0.1 -- 0.1 -db passband ripple (note 3) - - 0.05 -- 0.05 -- 0.05 db stopband (notes 2,3) 26.23 26.23 26.23 - - khz stopband attenuation (note 4) 60 - - 60 - - 60 - - db group delay (fs = input sample rate) tgd - 16 / fs - - 16 / fs - - 16 / fs - s interchannel isolation (1 khz) - 90 - - 90 - - 90 - db dc accuracy interchannel gain mismatch - 0.1 - - 0.1 - - 0.1 - db gain error - - 10 -- 10 -- 10 % gain drift - 250 - - 250 - - 250 - ppm/ c analog output full scale output voltage 3.33 3.70 4.07 1.66 1.85 2.03 3.33 3.70 4.07 vpp output common mode voltage - 2.3 - - 1.3 - - 2.3 - vdc minimum resistive load - 10 - - 10 - - 20 - k w maximum capacitive load - 100 - - 100 - - 100 - pf power supplies power supply current: normal operation power-down ia+ ia+ - - 28 60 32 - - - 20 20 25 - - - 28 60 32 - ma m a power dissipation normal operation power-down - - 140 0.3 160 - - - 60 0.06 75 - - - 140 0.3 160 - mw mw power supply rejection ratio (1 khz) psrr - 50 - - 50 - - 50 - db notes: 1. combined digital and analog filter characteristics. 2. the passband and stopband edges scale with frequency. for input sample rates, fs, other than 48 khz, the 0.05 db passband edge is 0.4535 fs and the stopband edge is 0.5465 fs. 3. digital filter characteristics. 4. measurement bandwidth is 10 hz to fs (khz) cs4330, cs4331, cs4333 2 ds136f1
switching characteristics (ta = 25 c; va+ = 2.7v - 5.5v; inputs: logic 0 = 0v, logic 1 = va+, cl = 20 pf) switching characteristics are guaranteed by characterization. parameter symbol min typ max units input sample rate fs 2 - 50 khz lrck duty cycle (external sclk only) (note 5) 30 50 70 % mclk pulse width high mclk / lrck = 512 10 - 1000 ns mclk pulse width low mclk / lrck = 512 15 - 1000 ns mclk pulse width high mclk / lrck = 384 21 - 1000 ns mclk pulse width low mclk / lrck = 384 21 - 1000 ns mclk pulse width high mclk / lrck = 256 35 - 1000 ns mclk pulse width low mclk / lrck = 256 39 - 1000 ns external sclk mode sclk pulse width low t sclkl 20 - - ns sclk pulse width high t sclkh 20 - - ns sclk period t sclkw 1 ( 128 ) fs --ns sclk rising to lrck edge delay t slrd 20 - - ns sclk rising to lrck edge setup time t slrs 20 - - ns sdata valid to sclk rising setup time t sdlrs 20 - - ns sclk rising to sdata hold time t sdh 20 - - ns internal sclk mode sclk period (note 6) t sclkw 1 sclk --ns sclk rising to lrck edge t sclkr - t sclkw 2 - m s sdata valid to sclk rising setup time t sdlrs 1 ( 512 ) fs + 15 --ns sclk rising to sdata hold time mclk / lrck = 256 or 512 t sdh 1 ( 512 ) fs + 15 --ns sclk rising to sdata hold time mclk / lrck = 384 t sdh 1 ( 384 ) fs + 15 --ns notes: 5. in internal sclk mode, the duty cycle must be 50% 1/2 mclk period. 6. the sclk / lrck ratio may be either 32, 48, or 64. cs4330, cs4331, cs4333 ds136f1 3
sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck external serial mode input timing sdata lrck mclk *internal sclk 1 n 2 n internal serial clock generation * the sclk pulses shown are internal to the cs4330/31/33. n equals mclk divided by sclk sdata **internal sclk *lrck sclkw t sdlrs t sdh t sclkr t internal serial mode input timing * lrck for cs4331 ** the sclk pulses shown are internal to the cs4330/31/33. cs4330, cs4331, cs4333 4 ds136f1
recommended operating conditions (agnd = 0v; all voltages with respect to ground) parameter symbol min typ max units dc power supply: (3v mode) va+ 2.7 3.0 4.0 v (5v mode) va+ 4.75 5.0 5.5 v digital characteristics (ta = 25 c; va+ = 2.7v - 5.5v) parameter symbol min typ max units high-level input voltage (va+ = 5.5v) v ih 2.4 - - v (va+ = 5.0v) v ih 2.0 - - v low-level input voltage v il --0.8v input leakage current (note 7) i in -- 10 m a notes: 7. i in for cs4331 lrck is 20 m a max. absolute maximum ratings (agnd = 0v; all voltages with respect to ground.) parameter symbol min max units dc power supply: va+ -0.3 6.0 v input current, any pin except supplies i in - 10 ma digital input voltage v ind -0.3 (va+)+0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. cs4330, cs4331, cs4333 ds136f1 5
dem/sclk 6 2.4k w audio data processor external clock mclk agnd aoutr cs4330 cs4331 cs4333 sdata lrck va+ aoutl 3 1 2 4 7 0.1 m f + 10 m f +3v/+5v 10 m f 8 c 56k w left audio output * * 2.4k w 10 m f 5 c 56k w right audio output * * * required for ac coupling only ** ** ** c = 1 (2 p )(2400 w )(fs)(2) + + figure 1. recommended connection diagram cs4330, cs4331, cs4333 6 ds136f1
general description the cs4330, cs4331, and cs4333 are complete stereo digital-to-analog systems including digital interpolation, 128 third-order delta-sigma digi- tal-to-analog conversion, digital de-emphasis and analog filtering, figure 2. this architecture pro- vides a high tolerance to clock jitter. the primary purpose of using delta-sigma modu- lation techniques is to avoid the limitations of laser trimmed resistive digital-to-analog con- verter architectures by using an inherently linear 1-bit digital-to-analog converter. the advantages of a 1-bit digital-to-analog converter include: ideal differential linearity, no distortion mecha- nisms due to resistor matching errors and no linearity drift over time and temperature due to variations in resistor values. digital interpolation filter the digital interpolation filter increases the sam- ple rate by a factor of 32 and is followed by a 4 digital sample-and-hold to effectively achieve a 128 interpolation filter. this filter eliminates images of the baseband audio signal which exist at multiples of the input sample rate, fs. this allows for the selection of a less complex analog filter based on out-of-band noise attenuation re- quirements rather than anti-image filtering. following the interpolation filter, the resulting frequency spectrum has images of the input sig- nal at multiples of 128 the input sample rate. these images are removed by the external ana- log filter. delta-sigma modulator the interpolation filter is followed by a third- order delta-sigma modulator which converts the 22-bit interpolation filter output into 1-bit data at 128 . switched-capacitor filter the delta-sigma modulator is followed by a digital-to-analog converter which translates the 1-bit data into a series of charge packets. the magnitude of the charge in each packet is deter- mined by sampling of a voltage reference onto a switched capacitor, where the polarity of each packet is controlled by the 1-bit signal. this technique greatly reduces the sensitivity to clock jitter and is a major improvement over earlier generations of 1-bit digital-to-analog converters. interpolator delta-sigma modulator dac analog low-pass filter analog output digital input figure 2. system block diagram cs4330, cs4331, cs4333 ds136f1 7
system design the cs4330/31/33 accept data at standard audio frequencies including 48 khz, 44.1 khz and 32 khz. audio data is input via the serial data input pin (sdata). the left/right clock (lrck) defines the channel and delineation of data and the serial clock (sclk) clocks audio data into the input data buffer. the cs4330, cs4331 and cs4333 differ in the serial data for- mat as shown in figures 4-7. the master clock (mclk) is used to operate the digital interpola- tion filter and the delta-sigma modulator. master clock the mclk must be either 256 , 384 , or 512 the desired input sample rate, fs. fs is the fre- quency at which words for each channel are input to the digital-to-analog converter, and is equal to the lrck frequency. the mclk to lrck frequency ratio is detected automatically during the initialization sequence by counting the number of mclk transitions during a single lrck period. internal dividers are set to gener- ate the proper clocks for the digital filter, delta-sigma modulator and switched-capacitor filter. table 1 illustrates several standard audio sample rates and the required mclk and lrck frequencies. serial clock the serial clock controls the shifting of data into the input data buffers. the cs4330/31/33 sup- port both external and internal serial clock generation modes. refer to figures 4-7 for data formats. external serial clock mode the cs4330/31/33 will enter the external serial clock mode when 4 low to high transitions are detected on the dem/sclk pin during any phase of the lrck period. when this mode is enabled, the internal serial clock mode and de- emphasis filter cannot be accessed. the cs4330/31/33 must return to power-down to exit this mode. refer to figure 8. internal serial clock mod e in the internal serial clock mode, the serial clock is internally derived and synchronous with mclk and lrck. the sclk/lrck frequency ratio is either 32, 48, or 64. operation in this mode is identical to operation with an external serial clock synchronized with lrck. this mode allows access to the digital de-emphasis function. refer to figure 8. while the internal serial clock mode is pro- vided to allow access to the de-emphasis filter, the internal serial clock mode also eliminates possible clock interference from an external sclk. use of internal serial clock mode is al- ways preferred, even when de-emphasis filtering is not required. de-emphasis the cs4330/31/33 include on-chip digital de- emphasis. figure 3 shows the de-emphasis curve for fs equal to 44.1 khz. the frequency re- sponse of the de-emphasis curve will scale proportionally with changes in sample rate, fs. the de-emphasis filter is active (inactive) if the dem/sclk pin is low (high) for 8 consecutive falling edges of lrck. this function is available only in the internal serial clock mode. lrck (khz) mclk (mhz) 256x 384x 512x 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760 table 1. common clock frequencies cs4330, cs4331, cs4333 8 ds136f1
initialization and power-down the initialization and power-down sequence flow chart is shown in figure 8. the cs4330/31/33 enter the power-down mode upon initial power- up. the interpolation filters and delta-sigma modulators are reset, and the internal voltage ref- erence, one-bit digital-to-analog converters and switched-capacitor low-pass filters are powered down. the device will remain in the power- down mode until mclk and lrck are presented. once mclk and lrck are detected, mclk occurrences are counted over one lrck period to determine the mclk/lrck frequency ratio. power is then applied to the internal volt- age reference and the +5 or +3 volt power supply mode is determined. finally, power is applied to the d/a converters and switched-ca- pacitor filters, and the analog outputs will move to approximately 2.3v (1.3v in 3v mode). this process requires approximately 1ms plus 1024 cycles of lrck. the cs4330/31/33 enter the power-down mode within 1 period of lrck if either mclk or lrck is removed. the initialization sequence begins when mclk and lrck are restored. if the mclk/lrck frequency ratio or the va+ voltage changes during power-down, the cs4330/31/33 adapt to these new operating con- ditions. it is recomended that the cs4330/31/33 not be powered up with the clocks (mclk, lrck, sclk) going. power supply determination the nominal power supply voltage for the cs4330/31/33 may be either +5 or +3 volts. "smart analog " circuitry senses the power supply voltage during the initialization sequence or when exiting the power-down mode. +5v op- eration will be set with a 3.7 vpp full scale output if va+ is between 4.75 and 5.5 volts. the cs4330/31/33 will be set for +3v operation with a 1.85 vpp full scale output if va+ is between 2.7 and 4.0 volts. supply voltages between 4.0 and 4.75 volts should be avoided to prevent op- eration in the 5v mode. in this condition there is insufficient headroom to produce a 3.7 vpp out- put. grounding and power supply decoupling as with any high resolution converter, the cs4330/31/33 require careful attention to power supply and grounding arrangements to optimize performance. figure 1 shows the recommended power arrangements with va+ connected to a clean +3/+5v supply. decoupling capacitors should be located as near to the cs4330/31/33 as possible. analog output and filtering the cs4330/31/33 analog filter is a switched-ca- pacitor filter. the switched-capacitor filter frequency response is clock dependent and will scale with sample rate. the digital filter of the cs4330/31/33 is de- signed to compensate for the magnitude and phase response of a single-pole low-pass filter at twice the sample rate. output filters consisting of a 2.4 kohm resistor and capacitor are recom- gain db -10db 0db frequency t2 = 15 m s t1=50 m s f1 f2 3.183 khz 10.61 khz figure 3. de-emphasis curve (fs = 44.1khz) cs4330, cs4331, cs4333 ds136f1 9
internal sclk mode external sclk mode right justified, 18-bit data data valid on rising edge of sclk int sclk = 64 fs if mclk/lrck = 256 or 512 int sclk = 48 fs if mclk/lrck = 384 right justified, 18-bit data data valid on rising edge of sclk sclk must have at least 36 cycles per lrck figure 4. cs4330 data format lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 internal sclk mode i 2 s, 16-bit data data valid on rising edge of sclk int sclk = 32 fs if mclk/lrck = 512 or 256 int sclk = 48 fs if mclk/lrck = 384 figure 5. cs4331 internal sclk data format (i 2 s) cs4330, cs4331, cs4333 10 ds136f1
lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 internal sclk mode external sclk mode right justified, 16-bit data data valid on rising edge of sclk int sclk = 32 fs if mclk/lrck = 512 or 256 int sclk = 48 fs if mclk/lrck = 384 right justified, 16-bit data data valid on rising edge of sclk sclk must have at least 32 cycles per lrck figure 7. cs4333 sclk data format lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 17 16 6543210 987 15 14 13 12 11 10 17 16 external sclk mode i 2 s, 18-bit data data valid on rising edge of sclk sclk must have at least 36 cycles per lrck figure 6. cs4331 external sclk data format (i 2 s) cs4330, cs4331, cs4333 ds136f1 11
user: apply power power-down mode user: apply mclk and lrck 256/384/512 mclk/lrck determination user: set sclk mode power supply determination +3 or +5 volt mode user: apply sdata sclk mode normal operation de-emphasis available normal operation de-emphasis not available user: apply sdata analog output is generated analog output is generated user: remove clocks user: remove clocks external internal figure 8. cs4330/31/33 initialization and power-down sequence cs4330, cs4331, cs4333 12 ds136f1
mended on the analog outputs. the required ca- pacitor value is defined by: c = 1 ( 2 p) ( fs ) ( 2400 w) ( 2 ) example: fs = 48 khz c = 690 pf a value of 680 pf may be used with only 1.45% error which is negligible. combined digital and analog filter response the frequency response of the combined analog switched-capacitor filter, digital filter, and off- chip single pole rc-filter at 2 fs, is shown in figures 9, 10, 11, and 12. the overall response is clock dependent and will scale with fs. note that the response plots have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. figure 9. cs4330/31/33 combined digital and analog filter stopband rejection figure 10. cs4330/31/33 combined digital and analog filter transition band figure 11. cs4330/31/33 combined digital and analog filter transition band figure 12. cs4330/31/33 combined digital and analog filter passband ripple cs4330, cs4331, cs4333 ds136f1 13
performance plots the following cs4330/31/33 measurement plots were taken on the cdb4330/31/33 evaluation board with an audio precision dual domain system one. all plots are done in +5v mode at a 48 khz sampling rate, and are shown in fig- ures 13-20. figure 13 shows the cs4330/31/33 frequency re- sponse. the response is flat to 20 khz 0.1db as specified. figure 14 shows thd+n versus signal ampli- tude for a 1 khz 20-bit dithered input signal. figure 15 shows a 16k fft of a 1 khz full-scale input signal. the signal has been filtered by a notch filter within the system one to remove the fundamental component of the signal. this mini- mizes the distortion created in the analyzer analog-to-digital converter. this technique is dis- cussed by audio precision in the 10th anniversary edition of audio.tst. figure 16 shows a 16k fft of a 1 khz -3 dbfs input signal. the signal has been filtered by a notch filter within the system one to remove the fundamental component of the signal. figure 17 shows a 16k fft of a 1 khz -20 dbfs input signal. the signal has been filtered by a notch filter within the system one to remove the fundamental component of the signal. figure 18 shows a 16k fft of a 1 khz -60 dbfs input signal. figure 19 shows a 16k fft of a 1 khz -90 dbfs input signal. figure 20 shows the fade-to-noise linearity. the input signal is a dithered 18-bit 500 hz sine figure 13. frequency response figure 14. thd+n vs. amplitude figure 15. 0 dbfs fft cs4330, cs4331, cs4333 14 ds136f1
wave which fades from -60 to -120 dbfs. dur- ing the fade, the output from the cs4330/31/33 is measured and compared to the ideal level. no- tice the very close tracking of the output level to the ideal, even at low level inputs. this indicates very good low-level linearity, one of the key benefits of delta-sigma digital-to-analog conver- sion. figure 19. -90 dbfs fft figure 20. fade-to-noise linearity figure 18. -60 dbfs fft figure 16. -3 dbfs fft figure 17. -20 dbfs fft cs4330, cs4331, cs4333 ds136f1 15
configuration register the cs4330, cs4331, cs4333 support multiple 2s-complement data/clock formats. the required format is governed by the contents of the con- figuration register. the 5-bit register determines which serial data format is acceptable, the fre- quency of the internal serial clock, on which edge of sclk audio data must be valid, and the number of bits to be loaded into the input buffer. on initial power-up, the register is loaded with the default settings, and it is not necessary to write to the register if this format is appropriate. the default settings are shown in figures 4-7. the 8-bit code includes a 3-bit preamble to pre- vent accidental access to the configuration register. each bit of the code is read on the fall- ing edge of lrck as shown in the figures 21 and 22. the code 01000000 is considered to be an error condition and is ignored. the configura- tion routine requires that the sdata pin is held high, as shown in figures 21 and 22, to prevent accidental writing to the register. the configura- tion register is only accessible prior to entering the external serial clock mode. for i 2 s mode, the user must set b6 to 0, and b7 to 1. b1 b2 b3 b4 b5 b6 b7 b8 b1 b2 b3 configuration access code 0 1 0 access allowed all other codes access denied b4 b5 internal sclk mode only sets internal sclk/lrck ratio * 0 0 sclk/lrck = 32 01 reserved 1 0 sclk/lrck = 64 1 1 sclk/lrck = 128 * the internal sclk will be 48 fs, if the mclk/lrck ratio is 384 . b4 b5 external sclk mode only selects data sampling edge of sclk 1 0 rising edge of sclk 1 1 falling edge of sclk b6 left or right justified data in relation to lrck transition 0 left justified 1 right justified b7 i 2 s data format 0disabled 1enabled b8 sets the number of bits 0 18 bits 1 16 bits schematic & layout review service confirm optimum schematic & layout before building your board. confirm optimum schematic & layout before building your board. for our free review service call applications engineering. for our free review service call applications engineering. call: (512) 445-7222 cs4330, cs4331, cs4333 16 ds136f1
figure 22. configuration timing figure 21. configuration operation parameter symbol min typ max units dem/sclk timing dem/sclk valid to lrck falling setup time t clrs 20 - - ns lrck falling to dem/sclk hold time t clrh 20 - - ns sdata setup time t setup 1- -us sdata hold time t hold 1- -us table 2. configuration timing characteristics cs4330, cs4331, cs4333 ds136f1 17
references 1)"an 18-bit, 8-pin stereo digital-to-analog converter" by j.j. paulos, a.w. krone, g.d kamath, and s.t. dupuie. paper presented at the 97th convention of the audio engineering soci- ety, november 1994. 2)"how to achieve optimum performance from delta-sigma a/d & d/a converters" by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. 3)"multiplier-free interpolation for oversampled digital-to-analog conversion" by jeffrey w. scott. paper presented at the 92nd convention of the audio engineering society, march 1992. 4)"an 18-bit stereo d/a converter with inte- grated digital and analog filters" by nav s. sooch, jeffrey w. scott. paper presented at the 91st convention of the audio engineering soci- ety, november 1991. 5)cdb4330/31/33 evaluation board data sheet; ds136db2 mar96 cs4330, cs4331, cs4333 18 ds136f1
pin descriptions power supply connections va+ - positive analog power, pin 7. positive analog supply. nominally +5v or +3v. agnd - analog ground, pin 6. analog ground reference. analog outputs aoutl - analog left channel output, pin 8. analog output for the left channel. typically 3.7 vpp for a full-scale input signal at va+ = 5v and 1.85 vpp at va+ = 3v. aoutr - analog right channel output, pin 5. analog output for the right channel. typically 3.7 vpp for a full-scale input signal at va+ = 5v and 1.85 vpp at va+ = 3v. digital inputs mclk - master clock input, pin 4. the frequency must be 256 , 384 , or 512 the input sample rate (fs). lrck - left/right clock, pin 3. this input determines which channel is currently being input on the audio serial data input pin, sdata. sdata - audio serial data input, pin 1. twos complement msb-first serial data is input on this pin. the data is clocked into the cs4330, cs4331, and cs4333 via internal or external sclk and the channel is determined by lrck. dem/sclk - de-emphasis / external serial clock input , pin 2. a dual-purpose input used for de-emphasis filter control or external serial clock input. serial data input sdata aoutl analog left channel output de-emphasis / sclk dem/sclk va+ analog power left / right clock lrck agnd analog ground master clock mclk aoutr analog right channel output 7 2 6 3 5 4 8 1 cs4330, cs4331, cs4333 ds136f1 19
parameter definitions total harmonic distortion + noise (thd+n) - the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range - the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering society, aes17-1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation - a measure of crosstalk between the left and right channels. measured for each channel at the converters output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch - the gain difference between left and right channels. units in decibels. gain error - the deviation from the nominal full scale analog output for a full scale digital input. gain drift - the change in gain value with temperature. units in ppm/ c. cs4330, cs4331, cs4333 20 ds136f1
ordering information : model temperature package cs4330-ks -10 to +70c 8-pin plastic soic cs4331-ks -10 to +70c 8-pin plastic soic cs4333-ks -10 to +70c 8-pin plastic soic CS4330-BS -40 to +85c 8-pin plastic soic cs4331-bs -40 to +85c 8-pin plastic soic cs4333-bs -40 to +85c 8-pin plastic soic f g j i h b a millimeters inches min max max min dim h i j a b typ 1.27 0.050 typ d 0 0.010 0 0.25 e 0.070 0.074 1.77 1.88 0.006 0.010 0.15 0.25 8 0 8 0 0.030 0.019 0.48 0.76 0.319 0.302 0.203 0.210 5.15 5.35 7.67 8.1 5.18 5.4 0.204 0.213 d c 8-pin soic e f 0.33 0.51 0.020 g c 0.013 package dimensions note: the eiaj package is not a standard jedec package size cs4330, cs4331, cs4333 ds136f1 21
? notes ?
features demonstrates recommended layout and grounding arrangements cs8412 receives aes/ebu, s/pdif, & eiaj-340 compatible digital audio digital and analog patch areas requires only a digital signal source and power supplies for a complete digital-to-analog-converter system general description the cdb4330/31/33 evaluation board is an excellent means for quickly evaluating the cs4330/31/33 18-bit, stereo d/a converter. evaluation requires an analog signal analyzer, a digital signal source and a power supply. analog outputs are provided via rca connec- tors for both channels. the cs8412 digital audio receiver i.c. provides the system timing necessary to operate the cs4330/31/33 and will accept aes/ebu, s/pdif, and eiaj-340 compatible audio data. the evaluation board may also be configured to accept external timing signals for op- eration in a user application during system development. ordering information: cdb4330, cdb4331, cdb4333 evaluation board for cs4330 / cs4331 / cs4333 cdb4330 cdb4331 cdb4333 digital audio input i/o for clocks and data cs8412 digital audio interface cs4330/31/33 analog filter crystal semiconductor corporation p.o. box 17847, austin, tx 78760 (512) 445-7222 fax: (512) 445 7581 mar 96 ds136db2 23 copyright ? crystal semiconductor corporation 1996 (all rights reserved)
cdb4330/31/33 system overview the cdb4330/31/33 evaluation board is an ex- cellent means of quickly evaluating the cs4330/31/33. the cs8412 digital audio inter- face receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. the evaluation board also allows the user to supply clocks and data through a 10-pin header for system develop- ment. the cdb4330/31/33 schematic has been parti- tioned into 5 schematics shown in figures 2 through 7. each partitioned schematic is repre- sented in the system diagram shown in figure 1. notice that the the system diagram also includes the interconnections between the partitioned schematics. cs4330/31/33 digital to analog converter a description of the cs4330/31/33 is included in the cs4330/31/33 data sheet. cs8412 digital audio receiver the system receives and decodes the standard s/pdif data format using a cs8412 digital audio receiver, figure 4. the outputs of the cs8412 include a serial bit clock, serial data, left-right clock (fsync), de-emphasis control and a 256fs master clock. the operation of the cs8412 and a discussion of the digital audio in- terface are included in the 1994 crystal semiconductor audio data book . during normal operation, the cs8412 operates in the channel status mode where the leds dis- play channel status information for the channel selected by the cslr/fck jumper. this allows the cs8412 to decode and supply the de-empha- sis bit from the digital audio interface for control of the cs4330/31/33 de-emphasis filter via pin 3, cc/f0, of the cs8412. when the error information switch is activated, the cs8412 operates in the error and frequency information mode. the information displayed by the leds can be decoded by consulting the cs8412 data sheet. if the error information switch is activated, and the cs4330/31/33 is in the internal serial clock mode, then it is likely that the de-emphasis control for the cs4330/31/33 will be erroneous and produce an incorrect audio output. encoded sample frequency information can be displayed provided a proper clock is being ap- plied to the fck pin of the cs8412. when an led is lit, this indicates a "1" on the corre- sponding pin located on the cs8412. when an led is off, this indicates a "0" on the corre- sponding pin. neither the l or r option of cslr/fck should be selected if the fck pin is being driven by a clock signal. the evaluation board has been designed such that the input can be either optical or coax, fig- ure 6. it is not necessary to select the active input. however, both inputs can not be driven si- multaneously . cs8412 data format the cs8412 data format can be set with jumpers m0, m1, m2, and m3. these formats are shown in the cs8412 datasheet found in the 1994 crys- tal semiconductor audio data book . the format selected must be compatible with the corre- sponding data format of the cs4330/31/33 shown in figures 4-7 of the cs4330/31/33 datasheet. the default settings for m0-m3 on the evaluation board are given in tables 2-4. the compatible data formats we have chosen for the cs8412 and cs4330/31/33 are: cs8412 format 6;cs4330 cs8412 format 2;cs4331 (external sclk only) cs8412 format 5;cs4333 (external sclk only) cdb4330, cdb4331, cdb4333 24 ds136db2
analog output filter the recommended single pole filter required for the cs4330/31/33 has been combined with a unity gain output buffer (see figure 2). the ana- log output filter uses a motorola mc33202 single supply, dual op-amp. the low pass filter corner frequency is located at 2 fs, or 88.2 khz and is calculated by: f = 1 ( 2 p) ( r 8 || r 9 ) ( c 29 ) f = 1 ( 2 p) ( 15 k w || 6.65 k w) ( 390 pf ) = 88.5 khz power supply circuitry power is supplied to the evaluation board by three binding posts (gnd, +5v, +3v/+5v), see figure 7. the +5v input supplies power to the +5 volt digital circuitry (vd+5), while the +3v/+5v input supplies power to the voltage level converter (vd+3/+5), and cs4330/31/33 (va+3/+5) for evaluation in either +3 or +5 volt mode. the op-amp is supplied from the analog supply (va+) which can be derived from either the +5v post (va+5) or the +3/+5v post (va+3/+5) depending upon which ferrite bead (l4 or l5) is installed. the evaluation board is configured with va+ derived from va+5 (l5 in- stalled). to derive va+ from the +3v/+5v post (va+3/+5), remove the ferrite bead at l5, and install it at l4. input/output for clocks and data the evaluation board has been designed to allow the interface to external systems via the 10-pin header, j1. this header allows the evaluation board to accept externally generated clocks and data. the schematic for the clock/data i/o is shown in figure 5. the 74hc243 transceiver functions as an i/o buffer where the clk source jumper determines if the transceiver operates as a transmitter or receiver. the transceiver operates as a transmitter with the clk source jumper in the 8412 position. lrck, sdata, and sclk from the cs8412 will be available on j1. j22 must be in the 0 po- sition and j23 must be in the 1 position for mclk to be an output and to avoid bus conten- tion on mclk. the transceiver operates as a receiver with the clk source jumper in the external posi- tion. lrck, sdata and sclk on j1 become inputs. the cs8412 must be removed from the evaluation board for operation in this mode. there are 2 options for the source of mclk in the external clock source mode. mclk can be an input with j23 in the 1 position and j22 in the 0 position. however, the recommended mode of operation is to generate mclk on the evaluation board. mclk becomes an output with lrck, sclk and sdata inputs. this technique insures that the cs4330/31/33 receives a jitter free clock to maximize performance. this can be accom- plished by installing a crystal oscillator into u5, see figure 4 (the socket for u5 is located within the footprint for the cs8412) and placing j22 in the 1 position and j23 in the 0 position. grounding and power supply decoupling the cs4330/31/33 requires careful attention to power supply and grounding arrangements to op- timize performance. figure 2 shows the recommended power arrangements. the cs4330/31/33 is positioned over the analog ground plane near the digital/analog ground plane split. these ground planes are connected elsewhere on the board. this layout technique is used to minimizing digital noise and to insure proper power supply matching/sequencing. the decoupling capacitors are located as close to the cs4330/31/33 as possible. extensive use of ground plane fill on both the analog and digital sections of the evaluation board yield large re- ductions in radiated noise effects. cdb4330, cdb4331, cdb4333 ds136db2 25
jumper purpose position function selected cslr/fck selects channel for cs8412 channel status information l see cs8412 data sheet for details r clock select selects source of system clocks and data *8412 cs8412 clock/data source ext external clock/data source j22 j23 selects mclk as input or output *0 *1 see input/output for clocks and data section of text m0 cs8412 mode select *low see cs8412 data sheet for details m1 *high m2 *high m3 *low sclk selects sclk mode int internal sclk mode *ext external sclk mode dem_8412 selects source of de- emphasis control *low cs8412 de-emphasis high de-emphasis input static high * default setting from factory table 2. cdb4330 jumper selectable options connector input/output signal present +5v input (vd+5v) for cs8412 and digital section input (va+) for analog output filter op-amp (configured for +5v) +3/+5v input (vd+3/+5v) for voltage level converter input (va+3/+5v) for cs4330/31/33 gnd input ground connection from power supply digital input input digital audio interface input via coax optical input input digital audio interface input via optical mclk, sclk, lrck input/output i/o for master, serial, and left/right clocks sdata input/output i/o for serial data aoutl output left channel analog output aoutr output right channel analog output table 1. system connections cdb4330, cdb4331, cdb4333 26 ds136db2
jumper purpose position function selected cslr/fck selects channel for cs8412 channel status information l see cs8412 data sheet for details r clock select selects source of system clocks and data *8412 cs8412 clock/data source ext external clock/data source j22 j23 selects mclk as input or output *0 *1 see input/output for clocks and data section of text m0 cs8412 mode select *low see cs8412 data sheet for details m1 *high m2 *low m3 *low sclk selects sclk mode int internal sclk mode (note 1) *ext external sclk mode (note 1) dem_8412 selects source of de- emphasis control *low cs8412 de-emphasis high de-emphasis input static high * default setting from factory note 1. the cs8412 output data format requires the cs4331 be in the external sclk mode table 3. cdb4331 jumper selectable options jumper purpose position function selected cslr/fck selects channel for cs8412 channel status information l see cs8412 data sheet for details r clock select selects source of system clocks and data *8412 cs8412 clock/data source ext external clock/data source j22 j23 selects mclk as input or output *0 *1 see input/output for clocks and data section of text m0 cs8412 mode select *high see cs8412 data sheet for details m1 *low m2 *high m3 *low sclk selects sclk mode int internal sclk mode (note 1) *ext external sclk mode (note 1) dem_8412 selects source of de- emphasis control *low cs8412 de-emphasis high de-emphasis input static high * default setting from factory note 1. the cs8412 output data format requires the cs4333 be in the external sclk mode table 4. cdb4333 jumper selectable options cdb4330, cdb4331, cdb4333 ds136db2 27
digital audio input fig 6 i/o for clocks and data fig 5 cs8412 digital audio interface rxn rxp mclk lrck sclk sdata fig 2 aoutl aoutr fig 2 fig 4 cs4330/31/33 power down fig 3 voltage level converter fig 3 mclk lrck sclk sdata analog filter figure 1. system block diagram and signal flow cdb4330, cdb4331, cdb4333 28 ds136db2
figure 2. cs4330/31/33 and connections cdb4330, cdb4331, cdb4333 ds136db2 29
figure 3. voltage level conversion and power down circuitry cdb4330, cdb4331, cdb4333 30 ds136db2
note: u2 and u5 cannot be installed simultaneously figure 4. cs8412 digital audio receiver connections cdb4330, cdb4331, cdb4333 ds136db2 31
figure 5. i/o interface for clocks and data optical toshiba part torx173 available through insight electronics figure 6. digital audio input cdb4330, cdb4331, cdb4333 32 ds136db2
figure 7. power supply cdb4330, cdb4331, cdb4333 ds136db2 33
figure 8. cdb4330/31/33 component side silkscreen cdb4330, cdb4331, cdb4333 34 ds136db2
figure 9. cdb4330/31/33 component side (top) cdb4330, cdb4331, cdb4333 ds136db2 35
figure 10. cdb4330/31/33 solder side (bottom) cdb4330, cdb4331, cdb4333 36 ds136db2
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advance product information describes products which are in development and subject to development changes. cirrus logic, inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. however, the information is s ubject to change without notice and is provided as is without warranty of any kind (express or implied). no responsibility is assumed by cirr us logic, inc. for the use of this information, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, trademarks, or trade secrets. no part of this publication may be copied, reprodu ced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). furthermor e, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trademarks and service marks can be found a t http://www.cir- rus.com.

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